Glossary (стр. 4 )

·  all operations, concerned with transformation record’s elements are executed with help of logical instructions.

Let’s consider a sequence of actions, which are to be performed for processing a given element of record. So, for processing an element is necessary:

°  To put the given element into the register;

°  By using operator mask, to obtain a bit mask;

°  To localize bits in the register with help of instruction and;

°  To shift bits of element to the junior digit places of the register.

Structure of machinery instruction.

Machinery instruction is a coded according certain rules order (indication) to the microprocessor for executing some operation or action.

Each instruction includes elements, which determine:

°  what is to be done? (an answer to this question gives an element, which is called Operation Code (OC) );

°  objects, which are to be processed ( operands );

°  how must be done? (these elements are types of operands, which are usually given indirectly).

Prefixes are not compulsory elements of machinery instruction, the length of each prefix is 1 byte. In the memory prefixes precede the instruction. Predestination of prefixes consists in modification of operations, executed by the instruction. There are following types of prefixes:

·  Prefix of segment substitution (exchange). In the direct form it points, which register is used by the given instruction for addressing: the stack or data. It undoes (отменяет) the choice of segment register on default. These prefixes have the following meanings: 2eh – substitution of the segment CS; 36h – substitution of segment SS; 3eh substitution DS; 26h – substitution ES.

·  Prefix of address capacity. It specifies the capacity of address (16 or 32 width; in the real address mode it is always 16 width ).

·  Prefix of operand capacity. It is analogous to the previous one but concerns an operand width.

·  Prefix of repetition. It is used for strings processing.

q  Operation Code. This is a compulsory element for the operation description. There are many instructions, to which several codes of operation correspond; each of codes reflects specifica

q  Byte of Addressing Mode (modr/m). The meaning of this byte determines the used form of operands addresses. Operands may be located in the memory, or in registers, if they are located in the memory, then this byte determines components (offset, base and index registers), which are used for calculation of the effective (efficient) address. The byte sib (Scale-Index-Base) is used in the protected mode.

There are tree types of the Byte of Addressing Mode:

For usual two-1. addresses instructions:

Bits	7	6	5	4	3	2	1	0
	mod	reg	r/m

2. For instructions, which work with segment registers:

Bits	7	6	5	4	3	2	1	0
	mod	0	rs	r/m

3. For instructions, which work with the secondary Operation Codes:

Bits	7	6	5	4	3	2	1	0
	mod	Secondary OC	r/m

°  The field mod (6-7 bits) determines the addressing mode. This field is used jointly with the field r/m: subject to the meaning of mod the microprocessor discerns meanings of bits 0-2 . For example, if mod = 00, it means that the field offset in the instruction is absent, and in this case the address of operand is determined by content of base or (and) index register. If mod = 11, it means that there are no operands in the memory, and they are stored in registers. The field Secondary OC determines either register, which is in the instruction on the place of the second operand, or possible extension of OC.

As an example let’s consider the 7-th string once more:

7 000C 8B DA mov bx, dx

OC Byte of

Addressing Mode (BAM)

DA =1101 1010

Bits	7	6	5	4	3	2	1	0
	1	1	o	1	1	0	1	0
	mod	reg	r/m

From the analysis of BAM it follows, that mod = 11 (register addressing), r/m = reg = 010 = DX, and reg = BX = 011.

q  The field index is used for storing a number of the index register, which is necessary for calculation of efficient address.

q  The field base is used for storing the base register, which is also necessary, as you know, for calculation of efficient address of operand.

q  The field of offset in the instruction is 8-th, 16-th or 32-nd signed integer, which represents partially or as a whole the meaning of the operand’s efficient address.

q  The field of direct operand, it represents 8-th, 16-th, or 32-nd direct operand.

tions of operation execution.

Definition of addressing mode.

Def. The mode of addressing is a procedure of searching operand(s) for the program execution.

If an instruction has got two operands, then for each of operands must be given a mode of addressing (these modes may be different). Operands may be located in different places: directly in the instruction’s code, in some of the registers, in the memory cell (in the last situation there are several possibilities of pointing out operand’s address).

Strictly speaking, modes of addressing are elements of microprocessor’s architecture, from one point of view, so, as they reflect installed in it possibilities of searching operands. But from the other side, the modes of addressing are designated by special manners in the Assembly language, and from this point of view they may be considered as a part of the language.

The Main Groups of Instructions and Modes of their execution.

92 instructions are used in the microprocessor 8086. These instructions may be divided into 9 functional groups: 1) data transfer; 2) input-output; 3) manipulations with a stack; 4) flags transfer; 5)arithmetical; 6) bits processing; 7) transfer of control; 8) the microprocessor control; 9) strings processing.

Instructions of the first three groups are called instructions of information exchange. The predestination of these instruction: copying or exchange by data and addresses between registers, memory cells or input-output ports. They have a preparatory-concluding character of operational resources and are used for the initial preparation of addresses and data, as well as storing the obtained results. The main instructions of this kind :

q mov destination(dst),source(src) – for copying bytes or words from the source into destination. All modes of operations, with an exception of pair of direct operands and pair of segment registers. The destination mustn’t be a direct operand or CS register.

q xchg operand_1, operand_2 – for the exchange by contents between two registers, or a register with a memory cell. Registers mustn’t be both segment registers.

q lea register, memory (Load Effective Address). With help of this instruction it is possible to calculate and load in one of the registers: AX, BX, CX, DX, SI, DI, BP or SP an efficient address (offset) of the pointed operand from the memory. The second operand may be some. For example:

.data

B1 db?

…….

. code

lea SI, B1

q lds register, memory or les register, memory (Load Register and DS or Load Register and ES, correspondingly). These instructions permit to load simultaneously segment register and one of the ALU’s registers. But in order to use these instructions, it is necessary to obtain preliminarily the meaning of the full pointer in some area of memory and after this to point in the instruction the name of this area of memory in the instructions. For example, if we wont to obtain the full address of data with name exmpl, we should determine in the program the pointer to the area of memory, where the cell with this data is located, i. e.

.data

exmpl dw 18

ful_exmpl dd exmpl ;(so, the cell, where the full address is ;located must be not less than 20 bits width).

The Main Formats of Two-Operands Instructions

1)  “REGISTER-REGISTER” (2 bytes)